ELEC2311 - Lecture 7

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ELEC2311 - Lecture 6
VHDL Modelling of Finite State Machines - Slides

Modelling FSMs in VHDL

There are many different ways to model a Finite State Machine in VHDL. A common approach is to use two VHDL processes:

List

• Clocked Process — stores present state in flip-flops and applies any reset or set controls.

• Combinational Process — uses inputs and present state to determine next state and outputs.

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Representing States in VHDL

We build our state representation at the top of our architecture; we define all the possible states in an enumerated type list (called state_type).

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Enumerated type is a custom data type defined by listing every valid (symbolic or numberical) value it can hold.

Then, declare our present state (PS) and next state (NS) signals using the enumerated state type we have declared.

-- General form: enumerated type listing the state names 
type state_type_name is (state_name_1, ..., state_name_n); 
signal state_signal_name : state_type_name; 

For example:

type state_type is (EVEN, ODD);
signal PS,NS : state_type;

Now we can assign a state from our list to these signals (e.g. PS <= EVEN), to implement the combinatorial logic for our design.

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FSM Modelling Examples

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An asynchronous reset is used to place the FSM in a known initial state.

Clocked Process Example:

begin 
  -- asynchronous reset
  if (RESET = '1') then
	PS <= INITIAL_STATE;
  elsif (rising_edge(CLK)) then
	PS <= NS;
  end if;

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There are many different ways to model a FSM. A distinct process could be used for the output logic, or everything could be written in one process.

Output Process Example:

-- Combinational process computes the output 
OUTPUT_LOGIC : process(PS) 
begin 
  case PS is 
    when S4           => Z <= '1'; 
    when S1 | S2 | S3 => Z <= '0'; 
  end case; 
end process OUTPUT_LOGIC;

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State Assignment

State assignment (also known as state encoding) is the mapping of each symbolic state name onto a binary code stored in flip-flops. The chosen encoding affects flip-flop count, combinational logic size, and maximum clock speed.

Encoding Scheme	Flip-flops for $n$ States	Key Notes
Binary	${\log }_2(n)$	Fewest flip-flops; more combinational logic to decode.
Gray	${\log }_2(n)$	Adjacent codes differ by exactly one bit.
One-hot	$n$	One flip-flop per state. HIGH when respective state is active.
Almost one-hot	$n-1$	Same as one-hot, but all LOW represents a state, saving a flip-flop.

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One-hot encoding is useful for scenarios where flip-flops are cheap, such as when using FPGAs.

Unused State Codes

If the number of required states isn’t a power of two, then some binary codes stored in the flip-flops may not correspond to any defined state. These are known as unused or illegal states.

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Even if number of states is a power of two, the synthesis tool may select an encoding that leaves some codes unused.

If the FSM enters an unused code, its subsequent behaviour may be unpredictable because the optimised next-state logic may not define transitions from that code.

Reset $\ne$ Recovery

Reset only sets the FSM’s initial state at start-up. It does not automatically pull the FSM back to a valid state if it strays into an illegal code mid-operation; dedicated safe-state logic is required.

Selecting the State Encoding in Quartus

Quartus normally auto-selects the state encoding method during synthesis. The directive syn_encoding can instead be used to request a particular encoding.

For example:

type state_type is (EVEN, ODD);
attribute syn_encoding : string;
attribute syn_encoding of state_type : TYPE IS "one-hot";

You can also provide the binary code for each state:

attribute syn_encoding of state_type : TYPE IS "00 01";

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To use our own state encoding, in Assignments > Settings, select Compiler Settings > Advanced Settings > State Machine Processing & change the value to User-Encoded

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ELEC2311 - Lecture 8