Asynchronous Presets and Clears
- We need a way to set the value of a flip-flop or latch regardless of other inputs (e.g. on start-up of a device)
Clear forces the output low regardless of the other inputs (S=0)
Preset forces the output high regardless of the other inputs (S=1)
Example for a D-latch:
- This is asynchronous doesn’t matter whether clock is low or high
Registers
- Registers can hold more data than individual flip-flops
- A -bit register consists of flip-flops and stores bits
Example internal circuitry of a 4-bit register:
- All the flip-flops share common Clock and Reset signals
- Common clock: data is loaded in parallel at same clock edge
- Common reset: all Flip-Flops are reset in parallel