Testbenches

Testbenches are a type of design verification technique commonly used for testing hardware description languages, software and hardware.

The design being verified is called the design under test (DUT).

The testbench applies input stimuli to the DUT and allows its outputs to be observed. More advanced testbenches can automatically check DUT outputs against expected results.

The set of input values applied is known as a test vector. They can be defined directly in the testbench .vhd file or stored in a separate text file.

Types of Testbenches

A Stimulus-Only Testbench generates and applies input signals to the DUT only. The DUT outputs must be manually checked. This method is useful for initial debugging and simple designs, but manual checking becomes inefficient as the number of test cases increase.

A Full Testbench automatically checks the DUT outputs and compares them with the expected outputs.

VHDL Testbenches

Testbenches for designs written in VHDL will also be written in VHDL.

VHDL template for a Testbench:

---

const current = dv.current();
 
if (current && current.file.tags.some(t => t.toLowerCase() === "#topic")) {
    const inlinks = current.file.inlinks;
 
    // Split backlinks: general notes vs. lecture notes
    const lectureLinks = inlinks.where(l => l.path.includes("/Lecture Notes/"));
    const otherLinks = inlinks.where(l => !l.path.includes("/Lecture Notes/"));
 
    if (otherLinks.length > 0) {
        dv.header(4, "Links To This Page");
        dv.list(otherLinks);
    }
 
    if (lectureLinks.length > 0) {
        dv.header(4, "Referenced In Lecture Notes");
        dv.list(lectureLinks);
    }
}