Entity

The Entity is where you define your input and output ports for a VHDL file.

ENTITY nand_gate IS
	PORT (
		a   : IN STD_LOGIC;
		b   : IN STD_LOGIC;
		z   : OUT STD_LOGIC
	) ;
END nand_gate;

• ? The code-block above defines the structure of this gate:

  

• ! But it does not have NAND functionality yet!

  • We must define this functionality in the architecture

---

const current = dv.current();
 
if (current && current.file.tags.some(t => t.toLowerCase() === "#topic")) {
    const inlinks = current.file.inlinks;
 
    // Split backlinks: general notes vs. lecture notes
    const lectureLinks = inlinks.where(l => l.path.includes("/Lecture Notes/"));
    const otherLinks = inlinks.where(l => !l.path.includes("/Lecture Notes/"));
 
    if (otherLinks.length > 0) {
        dv.header(4, "Links To This Page");
        dv.list(otherLinks);
    }
 
    if (lectureLinks.length > 0) {
        dv.header(4, "Referenced In Lecture Notes");
        dv.list(lectureLinks);
    }
}