ELEC2311 - Lecture 4

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ELEC2311 - Lecture 3
VHDL: Latches, Flip-flops, Registers - Slides

Latches vs Flip-Flops

• Latch stores data when clock is HIGH
• Flip-flop stores data when clock rises (or falls)

Asynchronous Preset and Clear/Reset

Clear/Reset forces the output low regardless of the other inputs.
Preset forces the output high regardless of the other inputs.

Synchronous $-$ requires clock to go high or low.
Asynchronous $-$ doesn’t matter whether clock is high or low.

D Latch Implementation in VHDL

We can use behavioural modelling to model a latch in VHDL:

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
 
ENTITY latch IS 
	PORT ( D, Clock : IN STD_LOGIC ; 
		   Q        : OUT STD_LOGIC ); 
END latch ;
 
ARCHITECTURE behavioral OF latch IS
BEGIN
	PROCESS ( D, Clock ) 
	BEGIN 
		IF Clock = '1' THEN 
			Q <= D ;
		END IF ;
	END PROCESS ;
END behavioral ; 

Note that, the incomplete specification of the IF-THEN statement causes the synthesised latch to store the previous state of ‘Q’. There is no need to include an ELSE Q <= Q statement. This is known as implicit memory.

Negative D Latch

To create a negative D latch, change Clock = ‘1’ to Clock = ‘0’

Implicit Memory

Signals in VHDL do not need to be assigned a value on every possible execution path of a combinational process. Instead, synthesis may infer a latch to retain its previous value known as implicit memory.

This simplifies creation of memory in logic design. However, this also poses the disadvantage of unwanted latches being generated when all of the options in a conditional sequential statement are not specified.

To avoid the generation of unexpected latches, you must assign every output in a combinational process through complete conditional branches or default assignments. Alternatively, cover all alternatives in a CASE statement.

D Flip-Flop Implementation in VHDL

We can use behavioural modelling to model a flip-flop in VHDL:

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
 
ENTITY flipflop IS
	PORT ( D, Clock : IN STD_LOGIC ;
		   Q        : OUT STD_LOGIC );
END flipflop ;
 
ARCHITECTURE behavioral2 OF flipflop IS
BEGIN
	PROCESS ( Clock )
	BEGIN
		IF Clock'EVENT AND Clock = '1' THEN
			Q <= D ; 
		END IF ;
	END PROCESS ;
END behavioral2 ;

Negative D Flip-flop

For a negative D flip-flop, change Clock = ‘1’ to Clock = ‘0’

'EVENT detects any transition (event) on the signal clock, but doesn’t specify the direction. It is a VHDL signal attribute; a special property that provides information about a signal.

Alternatively, you can use rising_edge(Clock) or falling_edge(Clock) to return TRUE for only a rising/falling edge signal.

IF rising_edge(Clock) THEN
	Q <= D ;
END IF ;

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You can additionally implement an asynchronous or synchronous reset by modifying our VHDL code.

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
 
ENTITY flipflop_ar IS
	PORT ( D, Resetn, Clock : IN STD_LOGIC ;
		   Q                : OUT STD_LOGIC );
END flipflop_ar ;
 
ARCHITECTURE behavioral OF flipflop_ar IS
BEGIN
	PROCESS ( Resetn, Clock )
	BEGIN
		IF Resetn = '0' THEN
			Q <= '0' ;
		ELSIF rising_edge(Clock) THEN
			Q <= D ;
		END IF ;
	END PROCESS ;
END behavioral ; 

To change the above code to a synchronous clock, move the Reset check inside the rising_edge check.

8-Bit Register Implementation in VHDL

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
 
ENTITY reg8 IS
	PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	       Resetn, Clock : IN STD_LOGIC ;
		   Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END reg8 ;
 
ARCHITECTURE behavioral OF reg8 IS
BEGIN
	PROCESS (Resetn, Clock)
	BEGIN
		IF Resetn = '0' THEN
			Q <= "00000000" ;
		ELSIF rising_edge(Clock) THEN
			Q <= D ;
		END IF ;
	END PROCESS ;
END behavioral ;

GENERIC Parameterisation in VHDL

Generics are used to parameterise a design entity which allows a component to be customised by creating a parameter in the ENTITY which can then be passed on to the ARCHITECTURE.
 
Format:

GENERIC (generic_name:type[:= default_value]);

 
For example, we can use GENERIC to create an N-bit register, where the user can define N inside the ARCHITECTURE. This is primarily useful in structural modelling.

-- Entity declaration
entity entity_name is
	generic (generic list);
	port (port list);
end entity_name
 
-- Component declaration
component component_name
	generic (generic_list);
	port (port_list);
end component;
 
-- Component instantiation
instance_label: component_name 
	generic map (generic_association_list) 
	port map (port_association_list); 

Note: no semicolon ; between generic map and port map!
 
Generic values cannot change while the circuit is operating. A generic value may be supplied when an entity or component is instantiated.

Dynamic Values with GENERIC

Given a GENERIC list with:
Init : std_logic_vector(N-1 downto 0) := "?";

We do not know how many values the logic_vector may have as N is dynamic. Thus, we use an OTHERS statement to assign all bits in the vector to a value.

? -> OTHERS => '0'

This ensures that all bits are defined for all values of N

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ELEC2311 - Lecture 5