ELEC2311

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Q6)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
ENTITY my_circuit IS
	PORT (A, B, C, D: IN STD_LOGIC;
		G: OUT STD_LOGIC);
END my_circuit;
 
ARCHITECTURE arch OF my_circuit IS
	SIGNAL E, F: STD_LOGIC
BEGIN
	<insert code>
END arch;

a)

E <= A AND B;
F <= E OR C;
G <= F AND D;

b)

process(A,B,E,C,D,F)
BEGIN
	E <= A AND B;
	F <= E OR C;
	G <= D AND F;
end.process;