ELEC2311 Lab 3

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2.1:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity DFF_POS is
    Port ( D   : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           Q   : out STD_LOGIC);
end DFF_POS;
 
architecture Behavioral of DFF_POS is
begin
    process(CLK)
    begin
        if rising_edge(CLK) then
            Q <= D;
        end if;
    end process;
end Behavioral;

Testbench:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity DFF_POS_tb is
end DFF_POS_tb;
 
architecture behavior of DFF_POS_tb is
 
    component DFF_POS
        Port ( D   : in  STD_LOGIC;
               CLK : in  STD_LOGIC;
               Q   : out STD_LOGIC);
    end component;
 
    signal D_tb   : STD_LOGIC := '0';
    signal CLK_tb : STD_LOGIC := '0';
    signal Q_tb   : STD_LOGIC;
 
    constant CLK_PERIOD : time := 20 ns;
 
begin
 
    -- Device under test
    UUT: DFF_POS port map (D => D_tb, CLK => CLK_tb, Q => Q_tb);
 
    -- Free-running clock
    clk_process : process
    begin
        CLK_tb <= '0';
        wait for CLK_PERIOD/2;
        CLK_tb <= '1';
        wait for CLK_PERIOD/2;
    end process;
 
    -- Stimulus, deliberately not synced to the clock edges
    stim_process: process
    begin
        D_tb <= '0';
        wait for 30 ns;
        D_tb <= '1';
        wait for 20 ns;
        D_tb <= '0';
        wait for 20 ns;
        D_tb <= '1';
        wait for 15 ns;
        D_tb <= '0';
        wait for 25 ns;
        D_tb <= '1';
        wait for 40 ns;
 
        wait;  -- halt simulation
    end process;
 
end behavior;

2.2:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity DFF_NEG is
    Port ( D   : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           Q   : out STD_LOGIC);
end DFF_NEG;
 
architecture Behavioral of DFF_NEG is
begin
    process(CLK)
    begin
        if falling_edge(CLK) then
            Q <= D;
        end if;
    end process;
end Behavioral;

Testbench:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity DFF_NEG_tb is
end DFF_NEG_tb;
 
architecture behavior of DFF_NEG_tb is
 
    component DFF_NEG
        Port ( D   : in  STD_LOGIC;
               CLK : in  STD_LOGIC;
               Q   : out STD_LOGIC);
    end component;
 
    signal D_tb   : STD_LOGIC := '0';
    signal CLK_tb : STD_LOGIC := '0';
    signal Q_tb   : STD_LOGIC;
 
    constant CLPERIOD : time := 20 ns;
 
begin
 
    -- Device under test
    UUT: DFF_NEG port map (D => D_tb, CLK => CLK_tb, Q => Q_tb);
 
    -- Free-running clock
    clk_process : process
    begin
        CLK_tb <= '0';
        wait for CLK_PERIOD/2;
        CLK_tb <= '1';
        wait for CLK_PERIOD/2;
    end process;
 
    -- Same stimulus as DFF_POS_tb
    stim_process: process
    begin
        D_tb <= '0';
        wait for 30 ns;
        D_tb <= '1';
        wait for 20 ns;
        D_tb <= '0';
        wait for 20 ns;
        D_tb <= '1';
        wait for 15 ns;
        D_tb <= '0';
        wait for 25 ns;
        D_tb <= '1';
        wait for 40 ns;
 
        wait;  -- halt simulation
    end process;
 
end behavior;