VHDL Entity

The Entity is where you define your input and output ports for a VHDL file.

ENTITY nand_gate IS
	PORT (
		a   : IN STD_LOGIC;
		b   : IN STD_LOGIC;
		z   : OUT STD_LOGIC
	) ;
END nand_gate;

• ? The code-block above defines the structure of this gate:

  

• ! But it does not have NAND functionality yet!

  • We must define this functionality in the architecture

---

await dv.view("Scripts/topic-backlinks");