Verification vs Testing
Verification determines whether a design meets its specification and occurs before fabrication.
Testing determines whether a design is functioning correctly and occurs after fabrication.
The Importance of Testing Circuits
Testing is needed because even correctly designed chips can come out of fabrication broken. Common causes include dust particles, manufacturing variations and packaging damage. Testing identifies defective or unreliable chips before they reach the consumer.
Defect -> Fault -> Error
We use a model to describe how a physical defect causes an observable error in a circuit.
- A physical defect (e.g. a short) occurs during manufacture.
- Creates a fault that impacts circuit model (e.g. signal stuck at
1).- That fault then leads to an observable consequence (e.g. when that signal should be
0) producing an error.
A fault only produces an observable error if the test applied exposes its effect at a point that can be observed. Otherwise, the fault can go undetected even if it impacts the circuit.
Fundamentals of Testing Circuits
A standard way to test digital circuits is to use a method similar to testbenching, where sample input test vectors are applied to a design under test (DUT), and the test outputs are compared to the expected outputs.
Simulated vs Production Tests
Testbenching is an example of fault simulation, which is performed before chip fabrication. It evaluates supplied test vectors; it does not generate new test vectors.
In addition to fault simulation, fabricated chips are subjected to production tests. This needs to be heavily optimised, as it incurs large overhead costs. Test time needs to be absolutely minimised.
The Issue with Exhaustive Testing
Exhaustive testing does not scale. The number of combinations for a circuit increases exponentially with every additional input. It would take an incredibly long time, even with the fastest automatic test equipment, to exhaustively test a large circuit.
Concept bq
Exhaustive functional testing is therefore impractical.
Instead, we must find the smallest set of test vectors that detects the largest possible number of faults.
Comment bq
Design for testability must be considered early to reduce test time and cost.
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