A fault model represents defects at an abstracted logic level. This makes analysis much easier and helps automate test pattern generation. Models do not identify the physical cause, they focus on fault detection only.
The most commonly studied fault model is the Stuck-at Fault model. It assumes selected wires are “stuck at” logic 0 or 1, independent of logic values on other signal lines.
Stuck-At Fault Model
A SA0 (0) or SA1 (1) fault can be modelled on any signal line in a circuit. The model assumes that blocks (e.g. gates, flip-flops) are fault free and only interconnecting wires are faulty.
Stuck-At is not a physical defect model. SA0 and SA1 does not mean a line is shorted or grounded. If a faulty line is applied a clashing logic value, it produces a logical error.
Fault Notation
- Each wire must be labelled with a number.
2. Identify the fault by its place (wire) and type (0 or 1).
AND Gate Faults Example
An AND gate can have 6 possible faults, where any wire has either a SA0 or SA1 fault. Note that, the faults 1/0, 2/0 and 3/0 are indistinguishable.
The list of faults for a AND gate are displayed in a fault table above.
Summary bq
In general, for a gate of inputs, there will be single faults for that gate (i.e. 2 # of wires).
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