We must account for the impact of defects on the overall cost of manufacturing both chips and the final integrated circuit.
Every faulty chip increases the cost of the remaining good chips.
Quote bq
\text{Good chip Cost}\ ($) = \frac{\text{Cost of fabricating wafer}}{\text{Yield} \times \text{\# of chips on wafer}}
Additionally, not all chips survive post-processing phase.
Comment bq
\text{IC Cost}\ ($) = \frac{\text{(Fabrication + Packaging + Testing) cost}}{\text{Final Test Yield}}
Defect Level
Defect level (DL) measures how many faulty chips remain among those that passed testing. Undetected faulty chips are known as test escapes.
A lower defect level indicates better outgoing product quality:
Catching Faults Late
The later a fault is left to be detected, the more expensive the cost. This is because faults get more difficult and expensive to detect, diagnose and correct after further assembly.
Rule of Ten
The rule of ten is a useful approximation that states the cost of addressing a fault may increase by about ten times at each successive level of production.
| Level | Relative cost |
|---|---|
| Wafer | 0.01 – 0.1 |
| Packaged chip | 0.1 – 1 |
| Board | 1 – 10 |
| System | 10 – 100 |
| Field | 100 – 1000 |
Comment bq
It is important to catch faults as early as possible along the production pipeline.
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